Hardware Child Block Incorrectly Connected to Parent System

Signals between a hardware IP and the parent system design are incorrectly connected causing security risks.


Individual hardware IP must communicate with the parent system in order for the product to function correctly and as intended. If implemented incorrectly, while not causing any apparent functional issues, may cause security issues. For example, if the IP should only be reset by a system-wide hard reset, but instead the reset input is connected to a software-triggered debug mode reset (which is also asserted during a hard reset), integrity of data inside the IP can be violated.


The following examples help to illustrate the nature of this weakness and describe methods or techniques which can be used to mitigate the risk.

Note that the examples here are by no means exhaustive and any given weakness may have many subtle varieties, each of which may require different detection methods or runtime controls.

Example One

Many SoCs use hardware to partition system resources between trusted and un-trusted entities. One example of this concept is the Arm TrustZone, in which the processor and all security-aware IP attempt to isolate resources based on the status of a privilege bit. This privilege bit is part of the input interface in all TrustZone-aware IP. If this privilege bit is accidentally grounded or left unconnected when the IP is instantiated, privilege escalation of all input data may occur.

// IP definitionmodule tz_peripheral(clk, reset, data_in, data_in_security_level, ...);input clk, reset;input [31:0] data_in;input data_in_security_level;...endmodule// Instantiation of IP in a parent systemmodule soc(...)...tz_peripheral u_tz_peripheral(.clk(clk),.rst(rst),.data_in(rdata),//Copy-and-paste error or typo grounds data_in_security_level (in this example 0=secure, 1=non-secure) effectively promoting all data to “secure”).data_in_security_level(1'b0),);...endmodule

In the Verilog code below, the security level input to the TrustZone aware peripheral is correctly driven by an appropriate signal instead of being grounded.

// Instantiation of IP in a parent systemmodule soc(...)...tz_peripheral u_tz_peripheral(.clk(clk),.rst(rst),.data_in(rdata),// This port is no longer grounded, but instead drive by the appropriate signal.data_in_security_level(rdata_security_level),);...endmodule

See Also

Integration Issues

Weaknesses in this category are those that arise due to integration of multiple hardware Intellectual Property (IP) cores, from System-on-a-Chip (SoC) subsystem intera...

Comprehensive CWE Dictionary

This view (slice) covers all the elements in CWE.

Weaknesses without Software Fault Patterns

CWE identifiers in this view are weaknesses that do not have associated Software Fault Patterns (SFPs), as covered by the CWE-888 view. As such, they represent gaps in...

Weaknesses Introduced During Implementation

This view (slice) lists weaknesses that can be introduced during implementation.

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